Investigation of dimensionality e ects on capacitorless memory and trench power MOSFET

Abstract

This thesis has dealt with two di erent problems solved with electronic device simulations (TCAD). The rst relates to the Trench power MOSFET device characterization, with particular attention to device breakdown voltage as a function of the device parameters. The second one is about the simulation of Zero capacitor DRAM devices. The trench structure analysis requires the use of a device simulator that implements the drift-di usion model with impact ionization model. For a better analysis results, the Trench structure is compared with the equivalent pn structure which shows similar trends in breakdown voltage, but slightly higher, due to the of the trench structure's absence that introduces an additional electric eld component anticipating the breakdown. For reference structure, the breakdown voltage depends only on drift region doping and length. Turning to Trench structure it can be noted that each Trench's shape parameter a ects the breakdown voltage, in particular: The distance between two structures in the trench does not a ect the calculation of the breakdown voltage. The Trench curvature radius and the oxide thickness are directly proportional to the breakdown voltage. The Trench width does not a ect the breakdown voltage. The trench length is the most important trench's parameter in order to evaluate a good model. A one-dimensional analytical model for pn structure has been presented using a maximum electrical eld value prediction as border condition for Poisson equation. The same model has been used for trench MOS devices using a correction factor for maximum electrical eld calculation based on trench penetration into drain region and on drain region length. The analytical model shows good results in comparison with simulation results for wide range simulations. For the Zero capacitor DRAM simulations, so called ZRAM devices, we have presented a simulation study aimed at understanding the operation mode, the potential performance in terms of READ sensitivity, programming windows and retention time, and the scalability of a double gate type II Z RAM cell with respect to the type I cells. We nd that the operations of a type II ZRAM cell can be implemented by changing simultaneously all electrode potentials and does not necessarily require an appropriate time sequence of bias voltages. Moreover, in the proposed operation mode, the excess charge is stored at the gate interfaces and not in the bulk body. This excess charge is a self consistent charge, created during the WRITE \1" phase by impaction ionization and BTBT at the drain side and de ned by the accumulation condition imposed by the gate bias during the HOLD phase. The independence of the stored charge on the particular WRITE \1" bias con guration allows an excellent determination and tuning of device performances by experiments and device simulations. Stored data is read by an asymmetrical bias con guration of the gate interfaces where the bottom gate interface works in a manner similar to the HOLD mode while the top gate interface works in a manner similar to the WRITE \1" mode but with a lower drain bias in order to avoid drain disturbs. The charge eventually stored at the bottom interface increases the bulk potential at the top interfaces which in order reduces the source-bulk energy barrier allowing a high READ current. Because of the exponential dependence of the READ current respect to the bulk potential a higher I1=I0 ratio is found respect to type I operation mode allowing higher READ sensitivity, programming windows and retention times. Data retention is limited by the leakage associated to the state \0" due to BTBT at the source/drain to bulk junctions. Except for device geometries with degraded SCEs (L<<W and/or tox) the time retention associated to the state \1" is in nity because the stored charge is the self consistent accumulation charge dictated by gate potentials. Extensive scaling analysis is done involving longitudinal and transversal geometrical parameters. Longitudinal scaling (L) is limited by SCEs which increase the bulk potential and reduce hole density hence the retention and the READ sensitivity of state \1". To compensate this e ect transversal scaling (W, tox) must be used. Moreover, longitudinal scaling increases the absolute value of READ currents. Transversal scaling reduces SCEs improving the performances of state \1", but the associated increase of BTBT reduces performances of state \0". Moreover transversal scaling reduces the absolute value of READ currents. The choice of longitudinal and transverse dimensions is a trade-o between speed, READ sensitivity, retention and programming windows. It is found that scaling limit of device length is around 15 nm which is lower respect to the 25nm found for type I operation mode.