Dual mode logic-based design of variable-precision arithmetic circuits

Abstract

The ever growing technological progress has an unquestionable impact on our society and, with the recent emergence of innovative technological paradigms, such as Internet of Things (IoT), Artificial Intelligence (AI), Virtual Reality (VR), 5G, Edge Computing, etc, it is expected that it will take a more and more dominant role in the coming decades. Obviously, the full development of all these new technologies requires the design of specialized hardware to faithfully and efficiently implement specific applications and services. In this sense, the demand of electronic circuits and systems with small area, flexible processing capability, high performance, and low energy consumption, has recently become one of the major concerns in different research areas, such as computing, communications, automation, etc. In this context, this thesis work entitled "DUAL MODE LOGIC-BASED DESIGN OF VARIABLE-PRECISION ARITHMETIC CIRCUITS" aims to provide a contribution in the research of new design solutions for energy-efficient computing platforms, while also keeping high performance. In this regard, several strategies can be explored at different design abstraction levels, from system-level down to device-level. Among these, the design of variable-precision arithmetic circuits is a well-known approach to achieve more energy-efficient computing platforms when dealing with lossy multimedia applications (e.g., audio/video/image processing) where a reduction of the operation precision can be typically tolerated under the acceptable accuracy loss. At the same time, other solutions can be implemented at both circuit- and logic-level. In this regard, a new logic 8 family, namely Dual Mode Logic (DML), has recently emerged as an alternative design methodology to the existing digital design techniques. It was originally proposed as a combination of CMOS static and dynamic logics to allow on-the-fly controllable switching at the gate level between static and dynamic operation modes according to system requirements, input-driven control, and/or by designer considerations. Such modularity typically offers greater performance/energy trade-off flexibility in the design and optimization of digital circuits, especially for applications with a flexible workload, such as in multi-precision arithmetic circuits. In this thesis work, the benefits of the DML design approach with respect to the standard CMOS style are first highlighted on a flexible circuit benchmarck, consisting of 10 levels of 11-stage NAND/NOR chains. In this case, the DML implementation takes advantage of its capability that allows operating in a combined (mixed) mode, i.e. working at the same time partly statically and partly dynamically, thus leading to fully exploit the benefits of the two DML operation modes for better energy-performance trade-offs. Then, the flexibility inherently offered by the DML is exploited to design a double-precision (8×8-bit or 16×16-bit) carry-save adder (CSA)-based array multiplier with the aim of demonstrating the potential in combining the two aforementioned design solutions (i.e., multi-precision computing and DML methodology) in the design and optimization of arithmetic circuits. As a matter of fact, the DML dual operation ability is potentially very attractive to efficiently trade performance and energy consumption between the operations at different precisions in on-demand multi-precision digital circuits. This occurs in the proposed DML multiplier working in a mixed operation mode, i.e., by employing the DML static and dynamic mode for lower- and higher-precision operations, respectively. On one hand, the use 9 of the dynamic mode for higher-precision operations ensures higher performance as compared to its standard static CMOS counterpart (16% gain on average) at the cost of higher energy consumption. On the other hand, such energy penalty is counterbalanced at lower-precision operations for which the static mode is enabled in the DML circuit. Overall, the adoption of the mixed operation mode in the proposed DML multiplier proves to be beneficial to achieve a better performance/energy trade-off with respect to the standard static CMOS implementation and to the cases when using the DML static or dynamic mode for both operations at the two different precisions. When compared to its CMOS counterpart, the proposed DML design operating in the mixed mode exhibits an average improvement of 15% in terms of energy-delay product (EDP) under wide-range supply voltage scaling. Such benefit is maintained over process-voltage-temperature (PVT) variations.